OpenJDK / amber / amber
changeset 41331:ec5e0ea52c77
8129376: SPECjvm98-client performance regression in 9-b66
Reviewed-by: kvn
| author | mcberg |
|---|---|
| date | Tue, 20 Sep 2016 16:50:37 -0700 |
| parents | 8b2580e63aa0 |
| children | a1ff82a6136a |
| files | hotspot/src/cpu/x86/vm/c1_LinearScan_x86.hpp hotspot/src/cpu/x86/vm/x86_32.ad |
| diffstat | 2 files changed, 10 insertions(+), 8 deletions(-) [+] |
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--- a/hotspot/src/cpu/x86/vm/c1_LinearScan_x86.hpp Tue Sep 20 16:34:45 2016 -0400 +++ b/hotspot/src/cpu/x86/vm/c1_LinearScan_x86.hpp Tue Sep 20 16:50:37 2016 -0700 @@ -100,9 +100,11 @@ inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) { int last_xmm_reg = pd_last_xmm_reg; +#ifdef _LP64 if (UseAVX < 3) { last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1; } +#endif if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::byte_reg)) { assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only"); _first_reg = pd_first_byte_reg;
--- a/hotspot/src/cpu/x86/vm/x86_32.ad Tue Sep 20 16:34:45 2016 -0400 +++ b/hotspot/src/cpu/x86/vm/x86_32.ad Tue Sep 20 16:50:37 2016 -0700 @@ -104,14 +104,14 @@ // // Empty fill registers, which are never used, but supply alignment to xmm regs // -reg_def FILL0( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next(2)); -reg_def FILL1( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next(3)); -reg_def FILL2( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next(4)); -reg_def FILL3( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next(5)); -reg_def FILL4( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next(6)); -reg_def FILL5( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next(7)); -reg_def FILL6( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next(8)); -reg_def FILL7( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next(9)); +reg_def FILL0( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad()); +reg_def FILL1( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad()); +reg_def FILL2( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad()); +reg_def FILL3( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad()); +reg_def FILL4( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad()); +reg_def FILL5( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad()); +reg_def FILL6( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad()); +reg_def FILL7( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad()); // Specify priority of register selection within phases of register // allocation. Highest priority is first. A useful heuristic is to