OpenJDK / jdk / hs
changeset 46953:39063b484ec2
8186611: s390: Add missing compiler barriers and fix assembler
Reviewed-by: goetz
| author | mdoerr |
|---|---|
| date | Wed, 23 Aug 2017 10:25:25 +0200 |
| parents | cf06abc2071c |
| children | 6ad56f307810 bf23b44664aa a13bd8c6b7a2 9119841280f4 |
| files | hotspot/src/cpu/s390/vm/assembler_s390.inline.hpp hotspot/src/cpu/s390/vm/compiledIC_s390.cpp hotspot/src/os_cpu/linux_s390/vm/atomic_linux_s390.hpp |
| diffstat | 3 files changed, 24 insertions(+), 21 deletions(-) [+] |
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--- a/hotspot/src/cpu/s390/vm/assembler_s390.inline.hpp Tue Aug 22 20:31:36 2017 +0000 +++ b/hotspot/src/cpu/s390/vm/assembler_s390.inline.hpp Wed Aug 23 10:25:25 2017 +0200 @@ -246,8 +246,8 @@ inline void Assembler::z_mvhhi( int64_t d1, Register b1, int64_t i2) { emit_48( MVHHI_ZOPC | uimm12( d1, 20, 48) | regz(b1, 16, 48) | simm16(i2, 32, 48)); } inline void Assembler::z_mvhi ( int64_t d1, Register b1, int64_t i2) { emit_48( MVHI_ZOPC | uimm12( d1, 20, 48) | regz(b1, 16, 48) | simm16(i2, 32, 48)); } inline void Assembler::z_mvghi( int64_t d1, Register b1, int64_t i2) { emit_48( MVGHI_ZOPC | uimm12( d1, 20, 48) | regz(b1, 16, 48) | simm16(i2, 32, 48)); } -inline void Assembler::z_mvhhi( const Address &d, int64_t i2) { assert(!d.has_index(), " no index reg allowed in MVHHI"); z_mvghi( d.disp(), d.baseOrR0(), i2); } -inline void Assembler::z_mvhi ( const Address &d, int64_t i2) { assert(!d.has_index(), " no index reg allowed in MVHI"); z_mvghi( d.disp(), d.baseOrR0(), i2); } +inline void Assembler::z_mvhhi( const Address &d, int64_t i2) { assert(!d.has_index(), " no index reg allowed in MVHHI"); z_mvhhi( d.disp(), d.baseOrR0(), i2); } +inline void Assembler::z_mvhi ( const Address &d, int64_t i2) { assert(!d.has_index(), " no index reg allowed in MVHI"); z_mvhi( d.disp(), d.baseOrR0(), i2); } inline void Assembler::z_mvghi( const Address &d, int64_t i2) { assert(!d.has_index(), " no index reg allowed in MVGHI"); z_mvghi( d.disp(), d.baseOrR0(), i2); } inline void Assembler::z_ex(Register r1, int64_t d2, Register x2, Register b2) { emit_32( EX_ZOPC | regz(r1, 8, 32) | uimm12(d2, 20, 32) | reg(x2, 12, 32) | regz(b2, 16, 32)); }
--- a/hotspot/src/cpu/s390/vm/compiledIC_s390.cpp Tue Aug 22 20:31:36 2017 +0000 +++ b/hotspot/src/cpu/s390/vm/compiledIC_s390.cpp Wed Aug 23 10:25:25 2017 +0200 @@ -105,15 +105,18 @@ NativeMovConstReg* method_holder = nativeMovConstReg_at(stub + NativeCall::get_IC_pos_in_java_to_interp_stub()); NativeJump* jump = nativeJump_at(method_holder->next_instruction_address()); +#ifdef ASSERT // A generated lambda form might be deleted from the Lambdaform // cache in MethodTypeForm. If a jit compiled lambdaform method // becomes not entrant and the cache access returns null, the new // resolve will lead to a new generated LambdaForm. - - assert(method_holder->data() == 0 || method_holder->data() == (intptr_t)callee() || callee->is_compiled_lambda_form(), + volatile intptr_t data = method_holder->data(); + volatile address destination = jump->jump_destination(); + assert(data == 0 || data == (intptr_t)callee() || callee->is_compiled_lambda_form(), "a) MT-unsafe modification of inline cache"); - assert(jump->jump_destination() == (address)-1 || jump->jump_destination() == entry, + assert(destination == (address)-1 || destination == entry, "b) MT-unsafe modification of inline cache"); +#endif // Update stub. method_holder->set_data((intptr_t)callee());
--- a/hotspot/src/os_cpu/linux_s390/vm/atomic_linux_s390.hpp Tue Aug 22 20:31:36 2017 +0000 +++ b/hotspot/src/os_cpu/linux_s390/vm/atomic_linux_s390.hpp Wed Aug 23 10:25:25 2017 +0200 @@ -105,7 +105,7 @@ //---< inputs >--- : [inc] "a" (inc) // read-only. //---< clobbered >--- - : "cc", "r0", "r2", "r3" + : "cc", "r0", "r2", "r3", "memory" ); } else { __asm__ __volatile__ ( @@ -120,7 +120,7 @@ //---< inputs >--- : [inc] "a" (inc) // read-only. //---< clobbered >--- - : "cc" + : "cc", "memory" ); } @@ -151,7 +151,7 @@ //---< inputs >--- : [inc] "a" (inc) // read-only. //---< clobbered >--- - : "cc", "r0", "r2", "r3" + : "cc", "r0", "r2", "r3", "memory" ); } else { __asm__ __volatile__ ( @@ -166,7 +166,7 @@ //---< inputs >--- : [inc] "a" (inc) // read-only. //---< clobbered >--- - : "cc" + : "cc", "memory" ); } @@ -214,7 +214,7 @@ : // : [inc] "a" (inc) // read-only. //---< clobbered >--- - : "cc", "r2", "r3" + : "cc", "r2", "r3", "memory" ); } else { __asm__ __volatile__ ( @@ -229,7 +229,7 @@ //---< inputs >--- : //---< clobbered >--- - : "cc" + : "cc", "memory" ); } } @@ -258,7 +258,7 @@ : // : [inc] "a" (inc) // read-only. //---< clobbered >--- - : "cc", "r2", "r3" + : "cc", "r2", "r3", "memory" ); } else { __asm__ __volatile__ ( @@ -273,7 +273,7 @@ //---< inputs >--- : //---< clobbered >--- - : "cc" + : "cc", "memory" ); } } @@ -317,7 +317,7 @@ : // : [inc] "a" (inc) // read-only. //---< clobbered >--- - : "cc", "r2", "r3" + : "cc", "r2", "r3", "memory" ); } else { __asm__ __volatile__ ( @@ -335,7 +335,7 @@ //---< inputs >--- : //---< clobbered >--- - : "cc" + : "cc", "memory" ); } } @@ -364,7 +364,7 @@ : // : [inc] "a" (inc) // read-only. //---< clobbered >--- - : "cc", "r2", "r3" + : "cc", "r2", "r3", "memory" ); } else { __asm__ __volatile__ ( @@ -382,7 +382,7 @@ //---< inputs >--- : //---< clobbered >--- - : "cc" + : "cc", "memory" ); } } @@ -420,7 +420,7 @@ //---< inputs >--- : [upd] "d" (xchg_val) // read-only, value to be written to memory //---< clobbered >--- - : "cc" + : "cc", "memory" ); return (jint)old; @@ -439,7 +439,7 @@ //---< inputs >--- : [upd] "d" (xchg_val) // read-only, value to be written to memory //---< clobbered >--- - : "cc" + : "cc", "memory" ); return (intptr_t)old; @@ -490,7 +490,7 @@ : [upd] "d" (xchg_val) , "0" (cmp_val) // Read-only, initial value for [old] (operand #0). // clobbered - : "cc" + : "cc", "memory" ); return (jint)old; @@ -508,7 +508,7 @@ : [upd] "d" (xchg_val) , "0" (cmp_val) // Read-only, initial value for [old] (operand #0). // clobbered - : "cc" + : "cc", "memory" ); return (jlong)old;