changeset 59351:571fa76449b8

8244170: [aarch64] correct instruction typo for dcps1/2/3 Summary: Replace dpcs with dcps Reviewed-by: adinn, phh
author xliu
date Tue, 19 May 2020 10:38:26 -0700
parents 6d2c3c2fcb43
children 98d450e6aabf
files src/hotspot/cpu/aarch64/aarch64-asmtest.py src/hotspot/cpu/aarch64/aarch64.ad src/hotspot/cpu/aarch64/assembler_aarch64.hpp
diffstat 3 files changed, 5 insertions(+), 5 deletions(-) [+]
line wrap: on
line diff
--- a/src/hotspot/cpu/aarch64/aarch64-asmtest.py	Tue May 19 10:11:13 2020 -0700
+++ b/src/hotspot/cpu/aarch64/aarch64-asmtest.py	Tue May 19 10:38:26 2020 -0700
@@ -979,7 +979,7 @@
 generate (CondBranchOp, ["EQ", "NE", "HS", "CS", "LO", "CC", "MI", "PL", "VS", "VC",
                         "HI", "LS", "GE", "LT", "GT", "LE", "AL", "NV" ])
 
-generate (ImmOp, ["svc", "hvc", "smc", "brk", "hlt", # "dpcs1",  "dpcs2",  "dpcs3"
+generate (ImmOp, ["svc", "hvc", "smc", "brk", "hlt", # "dcps1",  "dcps2",  "dcps3"
                ])
 
 generate (Op, ["nop", "eret", "drps", "isb"])
--- a/src/hotspot/cpu/aarch64/aarch64.ad	Tue May 19 10:11:13 2020 -0700
+++ b/src/hotspot/cpu/aarch64/aarch64.ad	Tue May 19 10:38:26 2020 -0700
@@ -15286,7 +15286,7 @@
 
   ins_encode %{
     if (is_reachable()) {
-      __ dpcs1(0xdead + 1);
+      __ dcps1(0xdead + 1);
     }
   %}
 
--- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp	Tue May 19 10:11:13 2020 -0700
+++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp	Tue May 19 10:38:26 2020 -0700
@@ -962,9 +962,9 @@
   INSN(smc, 0b000, 0, 0b11);
   INSN(brk, 0b001, 0, 0b00);
   INSN(hlt, 0b010, 0, 0b00);
-  INSN(dpcs1, 0b101, 0, 0b01);
-  INSN(dpcs2, 0b101, 0, 0b10);
-  INSN(dpcs3, 0b101, 0, 0b11);
+  INSN(dcps1, 0b101, 0, 0b01);
+  INSN(dcps2, 0b101, 0, 0b10);
+  INSN(dcps3, 0b101, 0, 0b11);
 
 #undef INSN