OpenJDK / jdk / jdk
changeset 57515:5dc3440be041
8234599: PPC64: Add support on recent CPUs and Linux for JEP-352
Reviewed-by: mbaesken, mdoerr, adinn
| author | gromero |
|---|---|
| date | Thu, 21 Nov 2019 17:10:26 -0300 |
| parents | ce6662089667 |
| children | 4d90b46f099c |
| files | src/hotspot/cpu/ppc/macroAssembler_ppc.cpp src/hotspot/cpu/ppc/macroAssembler_ppc.hpp src/hotspot/cpu/ppc/ppc.ad src/hotspot/cpu/ppc/stubGenerator_ppc.cpp src/hotspot/cpu/ppc/vm_version_ppc.cpp src/java.base/unix/native/libnio/ch/FileChannelImpl.c test/jdk/java/nio/MappedByteBuffer/PmemTest.java |
| diffstat | 7 files changed, 115 insertions(+), 7 deletions(-) [+] |
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--- a/src/hotspot/cpu/ppc/macroAssembler_ppc.cpp Thu Dec 19 15:23:57 2019 -0500 +++ b/src/hotspot/cpu/ppc/macroAssembler_ppc.cpp Thu Nov 21 17:10:26 2019 -0300 @@ -5063,3 +5063,22 @@ SkipIfEqualZero::~SkipIfEqualZero() { _masm->bind(_label); } + +void MacroAssembler::cache_wb(Address line) { + assert(line.index() == noreg, "index should be noreg"); + assert(line.disp() == 0, "displacement should be 0"); + assert(VM_Version::supports_data_cache_line_flush(), "CPU or OS does not support flush to persistent memory"); + // Data Cache Store, not really a flush, so it works like a sync of cache + // line and persistent mem, i.e. copying the cache line to persistent whilst + // not invalidating the cache line. + dcbst(line.base()); +} + +void MacroAssembler::cache_wbsync(bool is_presync) { + assert(VM_Version::supports_data_cache_line_flush(), "CPU or OS does not support sync related to persistent memory"); + // We only need a post sync barrier. Post means _after_ a cache line flush or + // store instruction, pre means a barrier emitted before such a instructions. + if (!is_presync) { + fence(); + } +}
--- a/src/hotspot/cpu/ppc/macroAssembler_ppc.hpp Thu Dec 19 15:23:57 2019 -0500 +++ b/src/hotspot/cpu/ppc/macroAssembler_ppc.hpp Thu Nov 21 17:10:26 2019 -0300 @@ -888,6 +888,8 @@ void sha256(bool multi_block); void sha512(bool multi_block); + void cache_wb(Address line); + void cache_wbsync(bool is_presync); // // Debugging
--- a/src/hotspot/cpu/ppc/ppc.ad Thu Dec 19 15:23:57 2019 -0500 +++ b/src/hotspot/cpu/ppc/ppc.ad Thu Nov 21 17:10:26 2019 -0300 @@ -2224,6 +2224,7 @@ if (!has_match_rule(opcode)) return false; + bool ret_value = true; switch (opcode) { case Op_SqrtD: return VM_Version::has_fsqrt(); @@ -2286,9 +2287,17 @@ case Op_UpperCase: case Op_Whitespace: return UseCharacterCompareIntrinsics; + + case Op_CacheWB: + case Op_CacheWBPreSync: + case Op_CacheWBPostSync: + if (!VM_Version::supports_data_cache_line_flush()) { + ret_value = false; + } + break; } - return true; // Per default match rules are supported. + return ret_value; // Per default match rules are supported. } const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) { @@ -15217,6 +15226,44 @@ ins_pipe(pipe_class_default); %} +instruct cacheWB(indirect addr) +%{ + match(CacheWB addr); + + ins_cost(100); + format %{ "cache writeback, address = $addr" %} + ins_encode %{ + assert($addr->index_position() < 0, "should be"); + assert($addr$$disp == 0, "should be"); + __ cache_wb(Address($addr$$base$$Register)); + %} + ins_pipe(pipe_class_default); +%} + +instruct cacheWBPreSync() +%{ + match(CacheWBPreSync); + + ins_cost(0); + format %{ "cache writeback presync" %} + ins_encode %{ + __ cache_wbsync(true); + %} + ins_pipe(pipe_class_default); +%} + +instruct cacheWBPostSync() +%{ + match(CacheWBPostSync); + + ins_cost(100); + format %{ "cache writeback postsync" %} + ins_encode %{ + __ cache_wbsync(false); + %} + ins_pipe(pipe_class_default); +%} + //----------PEEPHOLE RULES----------------------------------------------------- // These must follow all instruction definitions as they use the names // defined in the instructions definitions.
--- a/src/hotspot/cpu/ppc/stubGenerator_ppc.cpp Thu Dec 19 15:23:57 2019 -0500 +++ b/src/hotspot/cpu/ppc/stubGenerator_ppc.cpp Thu Nov 21 17:10:26 2019 -0300 @@ -3026,8 +3026,8 @@ address start = __ function_entry(); __ sha256 (multi_block); - __ blr(); + return start; } @@ -3037,8 +3037,36 @@ address start = __ function_entry(); __ sha512 (multi_block); - + __ blr(); + + return start; + } + + address generate_data_cache_writeback() { + const Register cacheline = R3_ARG1; + StubCodeMark mark(this, "StubRoutines", "_data_cache_writeback"); + address start = __ pc(); + + __ cache_wb(Address(cacheline)); __ blr(); + + return start; + } + + address generate_data_cache_writeback_sync() { + const Register is_presync = R3_ARG1; + Register temp = R4; + Label SKIP; + + StubCodeMark mark(this, "StubRoutines", "_data_cache_writeback_sync"); + address start = __ pc(); + + __ andi_(temp, is_presync, 1); + __ bne(CCR0, SKIP); + __ cache_wbsync(false); // post sync => emit 'sync' + __ bind(SKIP); // pre sync => emit nothing + __ blr(); + return start; } @@ -3594,6 +3622,12 @@ } #endif + // data cache line writeback + if (VM_Version::supports_data_cache_line_flush()) { + StubRoutines::_data_cache_writeback = generate_data_cache_writeback(); + StubRoutines::_data_cache_writeback_sync = generate_data_cache_writeback_sync(); + } + if (UseAESIntrinsics) { StubRoutines::_aescrypt_encryptBlock = generate_aescrypt_encryptBlock(); StubRoutines::_aescrypt_decryptBlock = generate_aescrypt_decryptBlock();
--- a/src/hotspot/cpu/ppc/vm_version_ppc.cpp Thu Dec 19 15:23:57 2019 -0500 +++ b/src/hotspot/cpu/ppc/vm_version_ppc.cpp Thu Nov 21 17:10:26 2019 -0300 @@ -195,6 +195,12 @@ intx cache_line_size = L1_data_cache_line_size(); + if (PowerArchitecturePPC64 >= 9) { + if (os::supports_map_sync() == true) { + _data_cache_line_flush_size = cache_line_size; + } + } + if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1; if (AllocatePrefetchStyle == 4) {
--- a/src/java.base/unix/native/libnio/ch/FileChannelImpl.c Thu Dec 19 15:23:57 2019 -0500 +++ b/src/java.base/unix/native/libnio/ch/FileChannelImpl.c Thu Nov 21 17:10:26 2019 -0300 @@ -112,9 +112,9 @@ if (map_sync) { // ensure - // 1) this is Linux on AArch64 or x86_64 - // 2) the mmap APIs are available/ at compile time -#if !defined(LINUX) || ! (defined(aarch64) || (defined(amd64) && defined(_LP64))) + // 1) this is Linux on AArch64, x86_64, or PPC64 LE + // 2) the mmap APIs are available at compile time +#if !defined(LINUX) || ! (defined(aarch64) || (defined(amd64) && defined(_LP64)) || defined(ppc64le)) // TODO - implement for solaris/AIX/BSD/WINDOWS and for 32 bit JNU_ThrowInternalError(env, "should never call map on platform where MAP_SYNC is unimplemented"); return IOS_THROWN;
--- a/test/jdk/java/nio/MappedByteBuffer/PmemTest.java Thu Dec 19 15:23:57 2019 -0500 +++ b/test/jdk/java/nio/MappedByteBuffer/PmemTest.java Thu Nov 21 17:10:26 2019 -0300 @@ -71,7 +71,7 @@ * @summary Testing NVRAM mapped byte buffer support * @run main/manual PmemTest * @requires (os.family == "linux") - * @requires ((os.arch == "x86_64")|(os.arch == "amd64")|(os.arch == "aarch64")) + * @requires ((os.arch == "x86_64")|(os.arch == "amd64")|(os.arch == "aarch64")|(os.arch == "ppc64le")) */ import java.io.File;