changeset 60062:b9529fcbbd33

8248219: aarch64: missing memory barrier in fast_storefield and fast_accessfield Reviewed-by: aph Contributed-by: songyaofei2@huawei.com
author fyang
date Sun, 28 Jun 2020 16:47:25 +0800
parents 754ec520eb4a
children 26d27e424109
files src/hotspot/cpu/aarch64/templateTable_aarch64.cpp
diffstat 1 files changed, 7 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- a/src/hotspot/cpu/aarch64/templateTable_aarch64.cpp	Fri Jul 03 19:05:00 2020 +0200
+++ b/src/hotspot/cpu/aarch64/templateTable_aarch64.cpp	Sun Jun 28 16:47:25 2020 +0800
@@ -2975,6 +2975,9 @@
   // access constant pool cache
   __ get_cache_and_index_at_bcp(r2, r1, 1);
 
+  // Must prevent reordering of the following cp cache loads with bytecode load
+  __ membar(MacroAssembler::LoadLoad);
+
   // test for volatile with r3
   __ ldrw(r3, Address(r2, in_bytes(base +
                                    ConstantPoolCacheEntry::flags_offset())));
@@ -3067,6 +3070,10 @@
 
   // access constant pool cache
   __ get_cache_and_index_at_bcp(r2, r1, 1);
+
+  // Must prevent reordering of the following cp cache loads with bytecode load
+  __ membar(MacroAssembler::LoadLoad);
+
   __ ldr(r1, Address(r2, in_bytes(ConstantPoolCache::base_offset() +
                                   ConstantPoolCacheEntry::f2_offset())));
   __ ldrw(r3, Address(r2, in_bytes(ConstantPoolCache::base_offset() +